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9.1
CVE-2025-51679: openRISC OR1200 may behave unexpectedly due to design mismatch
CVE-2025-51679 · published 1 month ago
Summary
The openRISC OR1200 processor core has a mismatch between its hardware description and the final circuit layout, which can cause it to act in unintended ways. This could affect any system that relies on the core for correct operation. Review the latest code revisions and apply any available patches or verify the design against the updated documentation.
Original advisory text
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior.
Severity
9.1
Critical
Exploitation
EPSS <1%
Type
CWE-1281Sequence of Processor Instructions Leads to Unexpected Behavior
Timeline
Published26 Aug 2026
Updated27 Sep 2026
First seen26 Aug 2026
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